ltc1100 1 1100fc the ltc 1100 is a high precision instrumentation amplifier using zero-drift techniques to achieve outstanding dc performance. the input dc offset is typically 1 v while the dc offset drift is typically 5nv/ c; a very low bias current of 65pa is also achieved. the ltc1100 is self-contained; that is, it achieves a differ- ential gain of 100 without any external gain setting resistor or trim pot. the gain linearity is 20ppm and the gain drift is 4ppm/ c. the ltc1100 operates from a single 5v supply up to 8v. the output typically swings 300mv from its power supply rails with a 10k load. an optional external capacitor can be added from pin 7 to pin 8 to tailor the device? 18khz bandwidth and to eliminate any unwanted noise pickup. the ltc1100 is also offered in a 16-pin surface mount package with selectable gains of 10 or 100. the ltc1100 is manufactured using linear technology? enhanced ltcmos tm silicon gate process. precision, zero-drift instrumentation amplifier offset voltage: 10 v max offset voltage drift: 100nv/ c max bias current: 65pa max offset current: 65pa max gain nonlinearity: 20ppm max gain error: 0.075% max cmrr: 90db 0.1hz to 10hz noise: 1.9 v p-p single 5v supply operation 8-pin minidip thermocouple amplifiers strain gauge amplifiers differential to single-ended converters single 5v supply, dc instrumentation amplifier ? in 0.1 f 0.01 f 1 2 3 4 8 7 6 5 v out v in v + = 5v v out = 100 [v in ?(? in )] ltc1100 ltc1100 ?ta01 ltcmos is a trademark of linear technology corporation features descriptio u applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation.
ltc1100 2 1100fc (note 1) absolute axi u rati gs w ww u ltc1100acn ltc1100cn/cj parameter conditions min typ max min typ max units gain error 0.01 0.05 0.01 0.075 % 0.10 0.150 % gain nonlinearity 3 8 3 20 ppm 12 30 12 60 ppm input offset voltage (note 2) 1 10 1 10 v input offset voltage drift (note 2) 5 100 5 100 nv/ c input noise voltage dc to 10hz, t a =25 c 1.9 1.9 v p-p input bias current 2.5 50 2.5 65 pa 120 135 pa input offset current 10 50 10 65 pa common mode rejection ratio v cm = 2.3v to ? 4.7v (note 3) 104 115 90 110 db power supply rejection ratio v s = 2.375v to 8v 120 105 db output voltage swing r l = 2k, v s = 8v 7.2 6.2 7.2 6.2 v r l = 10k, v s = 8v 7.7 7.5 7.7 7.5 v supply current 2.4 2.8 2.4 3.3 ma 3.4 4.0 3.4 4.5 ma internal sampling frequency 2.8 2.8 khz bandwidth 18 18 khz order part number LTC1100CSW order part number 1 2 3 4 5 6 7 8 top view sw package 16-lead plastic so wide 16 15 14 13 12 11 10 9 nc gnd ref g = 10 cmrr nc ? in v nc nc v out g = 10 comp nc v in v + nc 1 2 3 4 8 7 6 5 top view gnd ref cmrr ? in v v out comp v in v + n8 package 8-lead pdip the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, r l = 10k, c c = 1000pf, unless otherwise noted. consult ltc marketing for parts specified with wider operating temperature ranges. operating temperature range ltc1100m/am (obsolete) ........... ? 55 c to 125 c ltc1100c ......................................... ? 40 c to 85 c output short circuit duration ......................... indefinite storage temperature range ................ ? 65 c to 150 c total supply voltage (v + to v ? ) ............................. 18v input voltage ....................... (v + + 0.3v) to (v ? ? 0.3v) lead temperature (soldering, 10 sec)................. 300 c t jmax = 110 c, ja = 100 c/w ltc1100cn8 t jmax = 110 c, ja = 130 c/w j package 8-lead cerdip t jmax = 150 c, ja = 100 c/w obsolete package consider the n package for an alternate source ltc1100cj8 ltc1100amj8 ltc1100mj8 package/order i for atio uu w electrical characteristics
ltc1100 3 1100fc ltc1100amj (note 4) ltc1100mj parameter conditions min typ max min typ max units gain error 0.01 0.05 0.01 0.075 % 0.11 0.150 % gain nonlinearity 3 8 3 20 ppm 40 65 ppm input offset voltage (note 2) 1 10 1 10 v input offset voltage drift (note 2) 5 100 5 100 nv/ c input noise voltage dc to 10hz, t a =25 c 1.9 1.9 v p-p input bias current 5 50 5 65 pa 300 450 pa input offset current 80 120 pa common mode rejection ratio v cm = ? 4.7v to 2.3v 100 90 db power supply rejection ratio v s = 2.375v to 8v 115 95 db output voltage swing r l =10k , v s = 8v 7.4 7.4 7.4 7.4 v r l =2k, v s = 8v 7.0 6.0 7.0 6.0 v supply current 2.4 2.4 3.3 ma 4.2 4.6 ma internal sampling frequency 2.8 2.8 khz bandwidth 18 18 khz the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, r l = 10k, c c = 1000pf, unless otherwise noted. ltc1100acs LTC1100CSW parameter conditions min typ max min typ max units gain error t a =25 c, a v =100 0.01 0.05 0.01 0.075 % a v =100 0.10 0.150 % a v =10 0.01 0.04 0.01 0.060 % a v =10 0.10 0.150 % gain nonlinearity t a =25 c, a v =100 3 8 3 20 ppm a v =100 12 30 12 60 ppm a v =10 1 8 1 10 ppm a v =10 25 40 ppm input offset voltage (note 2) 1 10 1 10 v input offset voltage drift (note 2) 5 100 5 100 nv/ c input noise voltage dc to 10hz, t a =25 c 1.9 1.9 v p-p input bias current 2.5 50 2.5 65 pa 120 135 pa input offset current 10 50 10 65 pa common mode rejection ratio v cm = ? 4.7v to 2.3v, a v =100 104 115 90 110 db a v =10 95 85 db power supply rejection ratio v s = 2.375v to 8v 120 105 db the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, r l = 10k, c c = 1000pf, unless otherwise specified. electrical characteristics electrical characteristics
ltc1100 4 1100fc ltc1100acs LTC1100CSW parameter conditions min typ max min typ max units output voltage swing r l = 10k, v s = 8v 7.2 6.2 7.2 6.2 v r l = 2k, v s = 8v 7.7 7.5 7.7 7.5 v supply current 2.4 2.8 2.4 3.3 ma 3.4 4.0 3.4 4.5 ma internal sampling frequency 2.8 2.8 khz bandwidth g = 100 18 18 khz g = 10 180 180 khz note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: these parameters are guaranteed by design. thermocouple effects preclude measurement of these voltage levels in high speed automatic test systems. v os is measured to a limit determined by test equipment capability. note 3: see applications information, single supply operation. note 4: please consult linear technology marketing. gain error vs temperature gain, phase vs frequency gain nonlinearity vs temperature ltc1100 ?bd0 1 4 (v ) 6 r 99r 8 7 5 (v + ) r 2 3 99r 1 + + r = 2.5k 10 (v ) + ltc1100 ?bd02 7 (v ) 11 r 90r 15 14 r 6 9r ? + + 9r 13 4 2 90r 3 r = 2.5k note: for a voltage gain of 10v/v short pin 2 to 3, and pin 14 to 15. temperature ( c) ?0 gain error ( %) 0 0.01 0.02 0.03 ?5 0 25 50 ltc1100 ?tpc01 75 100 125 0.04 0.05 0.01 v s = 8v r l = 50k the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, r l = 10k, c c = 1000pf, unless otherwise noted. temperature ( c) ?0 gain nonlinearity (ppm) 0 5 10 15 ?5 0 25 50 ltc1100 ?tpc03 75 100 125 20 25 ? v s = 8v r l = 50k electrical characteristics block diagra s w typical perfor a ce characteristics uw frequency (hz) 15 differential gain (db) 20 25 30 35 100 10k 100k 1m ltc1100 ?tpc02 1k 40 30 60 90 120 150 180 (g = 100) gain phase phase shift (degrees) 45 10 5 0 ?0 210 gain (g = 10)
ltc1100 5 1100fc power supply rejection ratio common mode range supply current vs supply voltage vs frequency vs supply voltage undistorted output swing cmrr vs frequency output voltage swing vs load vs frequency bias current vs internal sampling frequency common mode voltage voltage noise vs frequency vs supply voltage load resistance (k ? ) 0 v out swing (v) 0 1 2 3 1234 ltc1100 ?tpc08 56 7 4 5 89 10 6 7 8 negative positive negative positive positive negative 9 10 v s = 8v, t a 85 c v s = 5v, t a 85 c v s = 2.5v, t a 85 c frequency (hz) 0.1 20 0 cmrr (db) 60 40 100 80 120 1 10 100 1k ltc1100 ?tpc07 10k 100k + 3 6 1 2 r c c c ltc1100 g = 100, r c = 100k c c = 10pf g = 10, r c = c c = 0pf g = 100, r c = c c = 0pf frequency (hz) 100 0 peak-to-peak output swing (v) 1 3 4 10 1k 10k 100k ltc1100 ?tpc09 2 5 6 7 8 9 r l = 100k r l = 2k v s = 5v common mode voltage (v) bias current (pa) 300 ?80 ?20 ?0 ? ? ? ? ltc1100 ?tpc10 ? 0 1 0 60 23 4 120 180 240 v s = 5v t a = 25 c t a = 125 c t a = 55 c ? 200 360 2 4 sampling frequency (khz) 1 2 61014 ltc1100 ?tpc12 4812 16 3 t a = 25 c t a = 55 c t a = 125 c 18 0 total supply voltage v + to v (v) frequency (hz) 0.1 power supply rejection ratio (db) 25 50 75 100 110 100 ltc1100 ?tpc05 1k 10k 100k 125 150 0 total supply voltage v + to v ? (v) 2 0 supply current (ma) 1 2 61014 ltc1100 ?tpc04 4812 16 3 4 t a = 55 c t a = 25 c t a = 125 c 18 supply voltage (v) ? common mode range (v) ? ? ? 0 2 8 2 4 6 8 ltc1100 ?tpc06 3 5 7 4 6 positive common mode range negative common mode range t a = 25 c frequency (hz) 15 voltage noise density (nv/ hz) 30 45 60 105 1k 10k 100k ltc1100 ?tpc11 100 75 90 0 10 typical perfor a ce characteristics uw
ltc1100 6 1100fc large-signal transient response small-signal transient response overload recovery g = 100, v s = 5v g = 100, v s = 5v g = 100, v s = 5v 8-pin dip (16-pin so) pin 1 (2) gnd ref: connect to system ground. this sets the zero reference for the internal op amps. pin 2 (4) cmrr: this pin tailors the gain of the internal amplifiers to maximize ac cmrr. for applications which emphasize cmrr requirements, connect a 100k resistor and a 10pf capacitor in series from cmrr to ground. see the applications section. pin 3 (6) ? in : inverting input. pin 4 (7) v ? : negative supply. pin 5 (10) v + : positive supply. pin 6 (11) v in : noninverting input. pin 7 (13) comp: this pin reduces the bandwidth of the internal amplifiers for applications at or near dc. clock feedthrough from the internal sampling clock can also be suppressed by using the comp pin. the standard com- pensation circuit is a capacitor from comp to v out , sized to provide an rc pole with the internal 247k resistor (22.5k for ltc1100cs in gain-of-10 mode). see the applications section. pin 8 (15) v out : signal output. 16-pin so package only (3) g = 10: short to pin (2) for gain of 10. leave dis connected for gain of 100. (14) g = 10: short to pin (15) for gain of 10. leave disconnected for gain of 100. note: both pins must be shorted or open to provide correct gain. (1),(5),(8),(9),(12),(16) nc : no internal connection. large-signal transient response small-signal transient response overload recovery g = 10 (ltc1100cs only), v s = 5v g = 10 (ltc1100cs only), v s = 5v g = 10 (ltc1100cs only), v s = 5v 1 s/div ltc1100 ?tpc18 ltc1100 ?tpc16 10 s/div 2v/div 10 s/div ltc1100 ?tpc17 50ms/div 10 s/div ltc1100 ?tpc13 10 s/div ltc1100 ?tpc14 5 s/div ltc1100 ?tpc15 1v/div 2v/div 50mv/div 2v/div 2v/div 1v/div typical perfor a ce characteristics uw uu u pi fu ctio s
ltc1100 7 1100fc common mode rejection due to very precise matching of the internal resistors, no trims are required to obtain a dc cmrr of better than 100db; however, things change as frequency rises. the inverting amplifier is in a gain of 1.01 (1.1 for gain of 10), while the noninverting amplifier is in a gain of 99 (9 for gain of 10). as frequency rises, the higher gain amplifier hits its gain-bandwidth limit long before the low gain amplifier, degrading cmrr. the solution is straightforward ?slow down the inverting amplifier to match the noninverting amp. figure 1 shows the recommended circuit. the prob- lem is less pronounced in the ltc1100cs in gain-of-10 mode; no cmrr trims are necessary. figure 2. overcompensation to reduce system bandwidth 100k 10pf 3 ltc1100 ?ta0 2 2 8 6 + ? + ? ltc1100 figure 1. improving ac cmrr overcompensation many instrumentation amplifier applications process dc or low frequency signals only; consequently, the 18khz (180khz for g = 10) bandwidth of the ltc1100 can be reduced to minimize system errors or reduce transmitted clock noise by using the comp pin. a feedback cap from comp to v out will react with the 247k internal resistor (22.5k for g = 10) to limit the bandwidth, as in figure 2. 3 ltc1100 ?ta03 8 6 + c 7 f = 3db 1 2 r c int r = 247k for g = 100 22.5k for g = 10 int b ltc1100 b aliasing the ltc1100 is a chopper-stabilized instrumentation amplifier; like all sampled systems it exhibits aliasing behavior for input frequencies at or near the internal sampling frequency. the ltc1100 incorporates special- ized anti-aliasing circuitry which typically attenuates aliasing products by 60db; however, extremely sensi- tive systems may still have to take precautions to avoid aliasing errors. for more information, see the ltc1051/ ltc1053 data sheet. single supply operation the ltc1100 will operate on a single 5v supply, and the common mode range of the internal op amps includes ground; single supply operation is limited only by the output swing of the op amps. the internal inverting amplifier has a negative saturation limit of 5mv typically, setting the minimum common mode limit at 5mv/1.01 (or 1.1 for gain of 10). the inputs can be biased above ground, as shown in figure 3. low cost biasing components can be used since any errors appear as a common mode term and are rejected. the minimum differential input voltage is limited by the swing of the output op amp. lightly loaded, it will swing down to 5mv, allowing differential input voltages as low as 50 v (450 v for gain of 10). single supply operation limits the ltc1100 to positive differential inputs only; negative inputs will give a saturated zero output. 3 5v ltc1100 ?ta0 4 8 6 ? + output 0v to 5v sensor r bias 5 4, 1 5v 1n4148 ltc1100 figure 3 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. applicatio s i for atio wu uu
ltc1100 8 1100fc lw/tp 1202 1k rev c ?printed in usa ? l inear technology corporation 1994 linear technology corporation 1 630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com j8 0801 .014 ?.026 (0.360 ?0.660) .015 ?.060 (0.381 ?1.524) .125 3.175 min .100 (2.54) bsc .300 bsc (7.62 bsc) .008 ?.018 (0.203 ?0.457) 0 ?15 .045 ?.065 (1.143 ?1.651) .045 ?.068 (1.143 ?1.650) full lead option .023 ?.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) .200 (5.080) max .005 (0.127) min .405 (10.287) max .220 ?.310 (5.588 ?7.874) 12 3 4 87 65 .025 (0.635) rad typ note: lead dimensions apply to solder dip/plate or tin plate leads j8 package 8-lead cerdip (narrow .300 inch, hermetic) (reference ltc dwg # 05-08-1110) n8 package 8-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) sw package 16-lead plastic small outline (wide .300 inch) (reference ltc dwg # 05-08-1620) obsolete package s16 (wide) 0502 note 3 .398 ?.413 (10.109 ?10.490) note 4 16 15 14 13 12 11 10 9 1 n 23 4 5 6 78 n/2 .394 ?.419 (10.007 ?10.643) .037 ?.045 (0.940 ?1.143) .004 ?.012 (0.102 ?0.305) .093 ?.104 (2.362 ?2.642) .050 (1.270) bsc .014 ?.019 (0.356 ?0.482) typ 0 ?8 typ note 3 .009 ?.013 (0.229 ?0.330) .005 (0.127) rad min .016 ?.050 (0.406 ?1.270) .291 ?.299 (7.391 ?7.595) note 4 45 .010 ?.029 (0.254 ?0.737) inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options. 4. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) .420 min .325 .005 recommended solder pad layout .045 .005 n 123 n/2 .050 bsc .030 .005 typ u package descriptio n8 1002 .065 (1.651) typ .045 ?.065 (1.143 ?1.651) .130 .005 (3.302 0.127) .020 (0.508) min .018 .003 (0.457 0.076) .120 (3.048) min 12 3 4 87 6 5 .255 .015* (6.477 0.381) .400* (10.160) max .008 ?.015 (0.203 ?0.381) .300 ?.325 (7.620 ?8.255) .325 +.035 ?015 + 0.889 0.381 8.255 () .100 (2.54) bsc note: 1. dimensions *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) inches millimeters are
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